This work presents the design, simulation, and layout of a fully differential low noise preamplifier for intracortical electroencephalography (iEEG) recording, implemented in TSMC 65 nm LP CMOS technology with a 1 V supply voltage. The circuit is intended as the first stage of an Analog Front-End (AFE) for an implantable device that records and transmits the information wirelessly. The AFE must amplify microvolt level neural signals while rejecting large electrode DC offsets, while meeting the provided power and area constraints. After reviewing existing architectures, the design was finally based on a Miller Compensated Capacitive Feedback Network (MCCFN) topology with a two stage operational transconductance amplifier (OTA). Input AC coupling through Metal/Insulator/Metal (MIM) capacitors blocks the DC electrode potential, and pseudo resistors implemented with thick oxide PMOS transistors set the high pass cutoff frequency below 1 Hz. AC, noise, and stability simulation tests were performed and then the layout implementation was made. The full chip tape-out is scheduled for July 7th.