Sub-1 V, 4 nA CMOS voltage references with digitally-trimmable temperature coefficient
Resumen:
Two architectures for MOS-only low power voltage references with digitally-trimmable temperature coefficient are proposed in this work. A test chip implements them in a 0.35 µm CMOS process. A design methodology for both architectures, performance figures and preliminary test results are presented. Each circuit consumes around 4 nA and operates down to 0.95 V or better with a simulated temperature coefficient of 18 ppm/° C in the -20°C to 80°C range.
| 2014 | |
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CMOS digital integrated circuits Low-power electronics Reference circuits Electrónica |
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| Inglés | |
| Universidad de la República | |
| COLIBRI | |
| https://hdl.handle.net/20.500.12008/41810 | |
| Acceso abierto | |
| Licencia Creative Commons Atribución - No Comercial - Sin Derivadas (CC - By-NC-ND 4.0) |
