A sub-µW intracranial EEG integrated preamplifier
Resumen:
This work presents an amplifier targeting the acquisition of intracranial electroencephalography signals with low power consumption, low voltage supply, low noise, and high common-mode rejection ratio (CMRR). A prototype was designed in a 180 nm FD-SOI CMOS technology and characterized by simulations. It presents an input noise of 3.2 µV rms , a current consumption of 0.5 µA, and it operates from a 1.8 V voltage supply, which represents a power consumption of 0.9 µW. The bandwidth ranges from 0.1 Hz to 1 kHz, the gain is 40 dB, the CMRR is greater than 79.4 dB, and the Noise Efficiency Factor (NEF) is 2.7.
| 2022 | |
| Este trabajo recibió apoyo de ANII, CSIC y CAP | |
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Semiconductor device modeling Low voltage Power demand Prototypes Voltage CMOS technology Brain modeling Analog integrated circuits Sub-threshold design EEG Low power DDA High CMRR |
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| Inglés | |
| Universidad de la República | |
| COLIBRI | |
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https://ieeexplore.ieee.org/document/9948541
https://hdl.handle.net/20.500.12008/34945 |
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| Acceso abierto | |
| Licencia Creative Commons Atribución - No Comercial - Sin Derivadas (CC - By-NC-ND 4.0) |
