A sub-µW intracranial EEG integrated preamplifier

 

Autor(es):

Cabrera, Carolina ; Oreggioni, Julián

Tipo:

Preprint

Versión:

Enviado

Financiadores:

Este trabajo recibió apoyo de ANII, CSIC y CAP

Resumen:

This work presents an amplifier targeting the acquisition of intracranial electroencephalography signals with low power consumption, low voltage supply, low noise, and high common-mode rejection ratio (CMRR). A prototype was designed in a 180 nm FD-SOI CMOS technology and characterized by simulations. It presents an input noise of 3.2 µV rms , a current consumption of 0.5 µA, and it operates from a 1.8 V voltage supply, which represents a power consumption of 0.9 µW. The bandwidth ranges from 0.1 Hz to 1 kHz, the gain is 40 dB, the CMRR is greater than 79.4 dB, and the Noise Efficiency Factor (NEF) is 2.7.

Año:

2022

Idioma:

Inglés

Temas:

Semiconductor device modeling
Low voltage
Power demand
Prototypes
Voltage
CMOS technology
Brain modeling
Analog integrated circuits
Sub-threshold design
EEG
Low power
DDA
High CMRR

Institución:

Universidad de la República

Repositorio:

COLIBRI

Enlace(s):

https://ieeexplore.ieee.org/document/9948541
https://hdl.handle.net/20.500.12008/34945

Nivel de acceso:

Acceso abierto