This thesis deals with the design of RF Power Ampliers (RFPAs) in nanometer CMOS technologies, in the context of ultra low power wireless applications. The current trend of designing CMOS RF Systems-on-Chip (SoCs) enables a new era of low cost RF systems. However, along with its benets of integration density and higher operation frequencies, nanometer CMOS processes present several challenges like strong process variability, that require a variability aware design. A method for designing RFPAs is presented, which aims to speed-up the design process and provide insight to the designer, by using a semiempirical MOSFET model extracted from simulations. The method considers transistor characteristics normalized to the transistor width (considering minimum length devices), and the parasitics of the passive components. This method was tested on IEEE 802.15.4/Bluetooth Low Energy 2.4 GHz compatible RFPAs in 90 nm CMOS. The measurements show that the characteristics can be accurately predicted and optimized, thus reducing design iterations. The fabricated designs also contribute to the state of the art showing that higher eciencies can be achieved. Due to the strong process variability a stringent RF production testing is required in nanometer CMOS. This has fueled the advent of RF Built-in-Self-Test (BiST), which intends to replace the external testing instruments with internal measurements, thus reducing costs. This technique is also encouraged by the availability of plenty of digital resources in current SoCs, which provide means to control and analyze the self test. Furthermore, the self test can lead to self healing by implementing Built-in-Self-Calibration (BiSC). In this work it was studied the RF Amplitude Detector block, which is fundamental for the implementation of BiST/BiSC. A novel method for modeling and optimizing a detector design is proposed, which is also based on semiempirical MOSFET models. Additionally, a new digital correction technique is also proposed, which allows extending the dynamic range with high tolerance to process variations. This technique relies in extensive statistical data obtained by simulations. The dynamic range extension was shown experimentally with several samples of a 90 nm design, showing that the detector area, power consumption and variability tolerance can be improved considerably. Finally, BiST and BiSC for an RFPA with minimal area and power overhead are experimentally demonstrated. This illustrates the convenience of these techniques in low-power wireless SoCs, a segment where, up to the best of our knowledge there are very few BiST/BiSC enabled systems.