MOSFET mismatch in weak/moderate inversion : model needs and implications for analog design
Resumen:
Based on mismatch measurements performed on very different CMOS technologies and large operating temperature range, we propose to model more adequately the mismatch in weak and moderate inversion by adding a new term related to the mismatch of the body effect factor dependence on the gate voltage. The model is introduced in a top-down analog design methodology, applied to the current mirror case, revealing some nonobvious design rules as well as typical misconceptions.
| 2003 | |
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MOSFET circuits Analog design Mismatch measurements ELECTRÓNICA |
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| Inglés | |
| Universidad de la República | |
| COLIBRI | |
| https://hdl.handle.net/20.500.12008/21263 | |
| Acceso abierto | |
| Licencia Creative Commons Atribución – No Comercial – Sin Derivadas (CC - By-NC-ND) |
| _version_ | 1807522961967546368 |
|---|---|
| author | Flandre, Denis |
| author2 | Serrano Gotarredona, T Linares-Barranco, B Silveira, Fernando Vancaillie, L |
| author2_role | author author author author |
| author_facet | Flandre, Denis Serrano Gotarredona, T Linares-Barranco, B Silveira, Fernando Vancaillie, L |
| author_role | author |
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| collection | COLIBRI |
| dc.creator.none.fl_str_mv | Flandre, Denis Serrano Gotarredona, T Linares-Barranco, B Silveira, Fernando Vancaillie, L |
| dc.date.accessioned.none.fl_str_mv | 2019-07-03T16:36:15Z |
| dc.date.available.none.fl_str_mv | 2019-07-03T16:36:15Z |
| dc.date.issued.es.fl_str_mv | 2003 |
| dc.date.submitted.es.fl_str_mv | 20190703 |
| dc.description.abstract.none.fl_txt_mv | Based on mismatch measurements performed on very different CMOS technologies and large operating temperature range, we propose to model more adequately the mismatch in weak and moderate inversion by adding a new term related to the mismatch of the body effect factor dependence on the gate voltage. The model is introduced in a top-down analog design methodology, applied to the current mirror case, revealing some nonobvious design rules as well as typical misconceptions. |
| dc.description.es.fl_txt_mv | Postprint Trabajo presentado en ESSCIRC 2004. 29th European Solid-State Circuits Conference, Estoril, Portugal, 2003 |
| dc.identifier.citation.es.fl_str_mv | Flandre, D, Serrano Gotarredona, T., Linares-Barranco, B., Silveira, F, Vancaillie, L. MOSFET mismatch in weak/moderate inversion : model needs and implications for analog design [en línea] ESSCIRC 2004. 29th European Solid-State Circuits Conference, Estoril, Portugal, 2003 |
| dc.identifier.uri.none.fl_str_mv | https://hdl.handle.net/20.500.12008/21263 |
| dc.language.iso.none.fl_str_mv | en eng |
| dc.publisher.es.fl_str_mv | ESSCIRC |
| dc.rights.license.none.fl_str_mv | Licencia Creative Commons Atribución – No Comercial – Sin Derivadas (CC - By-NC-ND) |
| dc.rights.none.fl_str_mv | info:eu-repo/semantics/openAccess |
| dc.source.none.fl_str_mv | reponame:COLIBRI instname:Universidad de la República instacron:Universidad de la República |
| dc.subject.es.fl_str_mv | MOSFET circuits Analog design Mismatch measurements |
| dc.subject.other.es.fl_str_mv | ELECTRÓNICA |
| dc.title.none.fl_str_mv | MOSFET mismatch in weak/moderate inversion : model needs and implications for analog design |
| dc.type.es.fl_str_mv | Artículo |
| dc.type.none.fl_str_mv | info:eu-repo/semantics/article |
| dc.type.version.none.fl_str_mv | info:eu-repo/semantics/publishedVersion |
| description | Postprint |
| eu_rights_str_mv | openAccess |
| format | article |
| id | COLIBRI_49948b2430a9c938b7746ad09894183f |
| identifier_str_mv | Flandre, D, Serrano Gotarredona, T., Linares-Barranco, B., Silveira, F, Vancaillie, L. MOSFET mismatch in weak/moderate inversion : model needs and implications for analog design [en línea] ESSCIRC 2004. 29th European Solid-State Circuits Conference, Estoril, Portugal, 2003 |
| instacron_str | Universidad de la República |
| institution | Universidad de la República |
| instname_str | Universidad de la República |
| language | eng |
| language_invalid_str_mv | en |
| network_acronym_str | COLIBRI |
| network_name_str | COLIBRI |
| oai_identifier_str | oai:colibri.udelar.edu.uy:20.500.12008/21263 |
| publishDate | 2003 |
| reponame_str | COLIBRI |
| repository.mail.fl_str_mv | mabel.seroubian@seciu.edu.uy |
| repository.name.fl_str_mv | COLIBRI - Universidad de la República |
| repository_id_str | 4771 |
| rights_invalid_str_mv | Licencia Creative Commons Atribución – No Comercial – Sin Derivadas (CC - By-NC-ND) |
| spelling | 2019-07-03T16:36:15Z2019-07-03T16:36:15Z200320190703Flandre, D, Serrano Gotarredona, T., Linares-Barranco, B., Silveira, F, Vancaillie, L. MOSFET mismatch in weak/moderate inversion : model needs and implications for analog design [en línea] ESSCIRC 2004. 29th European Solid-State Circuits Conference, Estoril, Portugal, 2003https://hdl.handle.net/20.500.12008/21263PostprintTrabajo presentado en ESSCIRC 2004. 29th European Solid-State Circuits Conference, Estoril, Portugal, 2003Based on mismatch measurements performed on very different CMOS technologies and large operating temperature range, we propose to model more adequately the mismatch in weak and moderate inversion by adding a new term related to the mismatch of the body effect factor dependence on the gate voltage. The model is introduced in a top-down analog design methodology, applied to the current mirror case, revealing some nonobvious design rules as well as typical misconceptions.Made available in DSpace on 2019-07-03T16:36:15Z (GMT). No. of bitstreams: 5 VSLSF03.pdf: 116629 bytes, checksum: 69bceaf1e38a307eb349fb221430b7a1 (MD5) license_text: 0 bytes, checksum: d41d8cd98f00b204e9800998ecf8427e (MD5) license_url: 49 bytes, checksum: 4afdbb8c545fd630ea7db775da747b2f (MD5) license_rdf: 0 bytes, checksum: d41d8cd98f00b204e9800998ecf8427e (MD5) license.txt: 4267 bytes, checksum: 6429389a7df7277b72b7924fdc7d47a9 (MD5) Previous issue date: 2003enengESSCIRCLas obras depositadas en el Repositorio se rigen por la Ordenanza de los Derechos de la Propiedad Intelectual de la Universidad De La República. (Res. Nº 91 de C.D.C. de 8/III/1994 – D.O. 7/IV/1994) y por la Ordenanza del Repositorio Abierto de la Universidad de la República (Res. Nº 16 de C.D.C. de 07/10/2014)info:eu-repo/semantics/openAccessLicencia Creative Commons Atribución – No Comercial – Sin Derivadas (CC - By-NC-ND)MOSFET circuitsAnalog designMismatch measurementsELECTRÓNICAMOSFET mismatch in weak/moderate inversion : model needs and implications for analog designArtículoinfo:eu-repo/semantics/articleinfo:eu-repo/semantics/publishedVersionreponame:COLIBRIinstname:Universidad de la Repúblicainstacron:Universidad de la RepúblicaFlandre, DenisSerrano Gotarredona, TLinares-Barranco, BSilveira, FernandoVancaillie, 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- Universidad de la Repúblicafalse |
| spellingShingle | MOSFET mismatch in weak/moderate inversion : model needs and implications for analog design Flandre, Denis MOSFET circuits Analog design Mismatch measurements ELECTRÓNICA |
| status_str | publishedVersion |
| title | MOSFET mismatch in weak/moderate inversion : model needs and implications for analog design |
| title_full | MOSFET mismatch in weak/moderate inversion : model needs and implications for analog design |
| title_fullStr | MOSFET mismatch in weak/moderate inversion : model needs and implications for analog design |
| title_full_unstemmed | MOSFET mismatch in weak/moderate inversion : model needs and implications for analog design |
| title_short | MOSFET mismatch in weak/moderate inversion : model needs and implications for analog design |
| title_sort | MOSFET mismatch in weak/moderate inversion : model needs and implications for analog design |
| topic | MOSFET circuits Analog design Mismatch measurements ELECTRÓNICA |
| url | https://hdl.handle.net/20.500.12008/21263 |
