This paper optimizes the design of an OTA for a Switched Capacitor (SC) Integrator in a discrete time Sigma-Delta Modulator based on the total settling time requirement and by application of the gm /Id method. One of the main constraints when implementing SC Sigma-Delta ADCs for high sampling rates is the requirement for the transition frequency and settling behavior of the operational transconductance amplifier. Extensive analysis has been carried out concerning the settling time, however an optimum regarding the distribution between the slew and linear periods is yet to be defined. The gm/ID method is used to sweep the design space of an OTA in order to find a minimum in power consumption thus an optimum slew/linear distribution. The method is validated through the design of three 2.5ns settling time OTAs for two design scenarios with different slew/linear distribution in a 130nm CMOS process. Results show that consumption savings of up to 60% are achieved when compared to the optimum design