Optimum nMOS/pMOS imbalance for energy efficient digital circuits
Resumen:
In this paper, we propose an asymmetrical length biasing scheme to be used in advanced nanometer technologies, which minimizes the energy per operation consumption of sub/near threshold digital CMOS circuits. Simulation results of two test circuits, a chain of inverters and a ripple carry adder, show that by using this sizing approach, the energy per operation can be reduced in more than 50% in a wide range of target performances. We use a 28-nm ultra-thin body and box fully depleted silicon-on-insulator technology and we show that the combination of supply voltage scaling, backplane biasing, and length biasing can be combined to obtain extremely robust (variability is almost halved) and energy efficient digital circuits. We also show simulation results for predictive technology models to show that the technique is also compatible with conventional bulk technologies
| 2017 | |
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Integrated circuit modeling MOS devices Transistors Mathematical model Leakage currents Digital circuits Low energy Asymmetric length biasing Poly biasing nMOS/pMOS imbalance Minimum energy point Electrónica |
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| Inglés | |
| Universidad de la República | |
| COLIBRI | |
| https://hdl.handle.net/20.500.12008/43535 | |
| Acceso abierto | |
| Licencia Creative Commons Atribución - No Comercial - Sin Derivadas (CC - By-NC-ND 4.0) |
| _version_ | 1807522942301503488 |
|---|---|
| author | Veirano Núñez, Francisco |
| author2 | Naviner, Lirida Silveira, Fernando |
| author2_role | author author |
| author_facet | Veirano Núñez, Francisco Naviner, Lirida Silveira, Fernando |
| author_role | author |
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| collection | COLIBRI |
| dc.creator.none.fl_str_mv | Veirano Núñez, Francisco Naviner, Lirida Silveira, Fernando |
| dc.date.accessioned.none.fl_str_mv | 2024-04-16T16:21:16Z |
| dc.date.available.none.fl_str_mv | 2024-04-16T16:21:16Z |
| dc.date.issued.es.fl_str_mv | 2017 |
| dc.date.submitted.es.fl_str_mv | 20240416 |
| dc.description.abstract.none.fl_txt_mv | In this paper, we propose an asymmetrical length biasing scheme to be used in advanced nanometer technologies, which minimizes the energy per operation consumption of sub/near threshold digital CMOS circuits. Simulation results of two test circuits, a chain of inverters and a ripple carry adder, show that by using this sizing approach, the energy per operation can be reduced in more than 50% in a wide range of target performances. We use a 28-nm ultra-thin body and box fully depleted silicon-on-insulator technology and we show that the combination of supply voltage scaling, backplane biasing, and length biasing can be combined to obtain extremely robust (variability is almost halved) and energy efficient digital circuits. We also show simulation results for predictive technology models to show that the technique is also compatible with conventional bulk technologies |
| dc.description.es.fl_txt_mv | Trabajo publicado en IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 64, no. 12 |
| dc.identifier.citation.es.fl_str_mv | Veirano, F, Naviner, L, Silveira, F. "Optimum nMOS/pMOS Imbalance for Energy Efficient Digital Circuits" Publicado en: IEEE Transactions on Circuits and Systems I: Regular Papers, v. 64, no. 12, pp. 3081-3091, 2017, doi: 10.1109/TCSI.2017.2747480 |
| dc.identifier.uri.none.fl_str_mv | https://hdl.handle.net/20.500.12008/43535 |
| dc.language.iso.none.fl_str_mv | en eng |
| dc.rights.license.none.fl_str_mv | Licencia Creative Commons Atribución - No Comercial - Sin Derivadas (CC - By-NC-ND 4.0) |
| dc.rights.none.fl_str_mv | info:eu-repo/semantics/openAccess |
| dc.source.none.fl_str_mv | reponame:COLIBRI instname:Universidad de la República instacron:Universidad de la República |
| dc.subject.es.fl_str_mv | Integrated circuit modeling MOS devices Transistors Mathematical model Leakage currents Digital circuits Low energy Asymmetric length biasing Poly biasing nMOS/pMOS imbalance Minimum energy point |
| dc.subject.other.es.fl_str_mv | Electrónica |
| dc.title.none.fl_str_mv | Optimum nMOS/pMOS imbalance for energy efficient digital circuits |
| dc.type.es.fl_str_mv | Artículo |
| dc.type.none.fl_str_mv | info:eu-repo/semantics/article |
| dc.type.version.none.fl_str_mv | info:eu-repo/semantics/publishedVersion |
| description | Trabajo publicado en IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 64, no. 12 |
| eu_rights_str_mv | openAccess |
| format | article |
| id | COLIBRI_12743f8ce86920a668942141218e3899 |
| identifier_str_mv | Veirano, F, Naviner, L, Silveira, F. "Optimum nMOS/pMOS Imbalance for Energy Efficient Digital Circuits" Publicado en: IEEE Transactions on Circuits and Systems I: Regular Papers, v. 64, no. 12, pp. 3081-3091, 2017, doi: 10.1109/TCSI.2017.2747480 |
| instacron_str | Universidad de la República |
| institution | Universidad de la República |
| instname_str | Universidad de la República |
| language | eng |
| language_invalid_str_mv | en |
| network_acronym_str | COLIBRI |
| network_name_str | COLIBRI |
| oai_identifier_str | oai:colibri.udelar.edu.uy:20.500.12008/43535 |
| publishDate | 2017 |
| reponame_str | COLIBRI |
| repository.mail.fl_str_mv | mabel.seroubian@seciu.edu.uy |
| repository.name.fl_str_mv | COLIBRI - Universidad de la República |
| repository_id_str | 4771 |
| rights_invalid_str_mv | Licencia Creative Commons Atribución - No Comercial - Sin Derivadas (CC - By-NC-ND 4.0) |
| spelling | 2024-04-16T16:21:16Z2024-04-16T16:21:16Z201720240416Veirano, F, Naviner, L, Silveira, F. "Optimum nMOS/pMOS Imbalance for Energy Efficient Digital Circuits" Publicado en: IEEE Transactions on Circuits and Systems I: Regular Papers, v. 64, no. 12, pp. 3081-3091, 2017, doi: 10.1109/TCSI.2017.2747480https://hdl.handle.net/20.500.12008/43535Trabajo publicado en IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 64, no. 12In this paper, we propose an asymmetrical length biasing scheme to be used in advanced nanometer technologies, which minimizes the energy per operation consumption of sub/near threshold digital CMOS circuits. Simulation results of two test circuits, a chain of inverters and a ripple carry adder, show that by using this sizing approach, the energy per operation can be reduced in more than 50% in a wide range of target performances. We use a 28-nm ultra-thin body and box fully depleted silicon-on-insulator technology and we show that the combination of supply voltage scaling, backplane biasing, and length biasing can be combined to obtain extremely robust (variability is almost halved) and energy efficient digital circuits. We also show simulation results for predictive technology models to show that the technique is also compatible with conventional bulk technologiesMade available in DSpace on 2024-04-16T16:21:16Z (GMT). No. of bitstreams: 5 VNS17.pdf: 1048412 bytes, checksum: 8c21c5738fe8f5cfa7e7eac3cb709970 (MD5) license_text: 21936 bytes, checksum: 9833653f73f7853880c94a6fead477b1 (MD5) license_url: 49 bytes, checksum: 4afdbb8c545fd630ea7db775da747b2f (MD5) license_rdf: 23148 bytes, checksum: 9da0b6dfac957114c6a7714714b86306 (MD5) license.txt: 4244 bytes, checksum: 528b6a3c8c7d0c6e28129d576e989607 (MD5) Previous issue date: 2017enengLas obras depositadas en el Repositorio se rigen por la Ordenanza de los Derechos de la Propiedad Intelectual de la Universidad De La República. (Res. Nº 91 de C.D.C. de 8/III/1994 – D.O. 7/IV/1994) y por la Ordenanza del Repositorio Abierto de la Universidad de la República (Res. Nº 16 de C.D.C. de 07/10/2014)info:eu-repo/semantics/openAccessLicencia Creative Commons Atribución - No Comercial - Sin Derivadas (CC - By-NC-ND 4.0)Integrated circuit modelingMOS devicesTransistorsMathematical modelLeakage currentsDigital circuitsLow energyAsymmetric length biasingPoly biasingnMOS/pMOS imbalanceMinimum energy pointElectrónicaOptimum nMOS/pMOS imbalance for energy efficient digital circuitsArtículoinfo:eu-repo/semantics/articleinfo:eu-repo/semantics/publishedVersionreponame:COLIBRIinstname:Universidad de la Repúblicainstacron:Universidad de la RepúblicaVeirano Núñez, FranciscoNaviner, LiridaSilveira, FernandoElectrónicaMicroelectrónicaLICENSElicense.txttext/plain4244http://localhost:8080/xmlui/bitstream/20.500.12008/43535/5/license.txt528b6a3c8c7d0c6e28129d576e989607MD55CC-LICENSElicense_textapplication/octet-stream21936http://localhost:8080/xmlui/bitstream/20.500.12008/43535/2/license_text9833653f73f7853880c94a6fead477b1MD52license_urlapplication/octet-stream49http://localhost:8080/xmlui/bitstream/20.500.12008/43535/3/license_url4afdbb8c545fd630ea7db775da747b2fMD53license_rdfapplication/octet-stream23148http://localhost:8080/xmlui/bitstream/20.500.12008/43535/4/license_rdf9da0b6dfac957114c6a7714714b86306MD54ORIGINALVNS17.pdfapplication/pdf1048412http://localhost:8080/xmlui/bitstream/20.500.12008/43535/1/VNS17.pdf8c21c5738fe8f5cfa7e7eac3cb709970MD5120.500.12008/435352024-07-24 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- Universidad de la Repúblicafalse |
| spellingShingle | Optimum nMOS/pMOS imbalance for energy efficient digital circuits Veirano Núñez, Francisco Integrated circuit modeling MOS devices Transistors Mathematical model Leakage currents Digital circuits Low energy Asymmetric length biasing Poly biasing nMOS/pMOS imbalance Minimum energy point Electrónica |
| status_str | publishedVersion |
| title | Optimum nMOS/pMOS imbalance for energy efficient digital circuits |
| title_full | Optimum nMOS/pMOS imbalance for energy efficient digital circuits |
| title_fullStr | Optimum nMOS/pMOS imbalance for energy efficient digital circuits |
| title_full_unstemmed | Optimum nMOS/pMOS imbalance for energy efficient digital circuits |
| title_short | Optimum nMOS/pMOS imbalance for energy efficient digital circuits |
| title_sort | Optimum nMOS/pMOS imbalance for energy efficient digital circuits |
| topic | Integrated circuit modeling MOS devices Transistors Mathematical model Leakage currents Digital circuits Low energy Asymmetric length biasing Poly biasing nMOS/pMOS imbalance Minimum energy point Electrónica |
| url | https://hdl.handle.net/20.500.12008/43535 |
