A compact functional verification flow for a RISC-V 321 based core
Resumen:
The structure of a functional verification flow used for the design of a RISC-V core is presented. The paper offers a guide on the test-planning used and details of the flow architecture, showing how to integrate the Universal Verification Methodology with the required, reference models, while implementing key futures in standard verification environments, such as testing regressions and code and structural coverage. The designed flow is compact yet efficient, making it affordable for small design teams, without requiring extra investment other than the already necessary licenses for RTL synthesis and the eventual fabrication of the chip.
| 2020 | |
| Agencia Nacional de Investigación e Innovación | |
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Functional verification RISC-V 321 UVM System Verilog EDA tools Architecture Test generation Compiler Processor Simulation Coverage Regression Reference model |
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| Inglés | |
| Universidad Católica del Uruguay | |
| LIBERI | |
| https://hdl.handle.net/10895/1549 | |
| Acceso abierto | |
| Licencia Creative Commons Atribución – No Comercial – Sin Derivadas (CC BY-NC-ND 4.0) |
