A compact functional verification flow for a RISC-V 321 based core
Resumen:
The structure of a functional verification flow used for the design of a RISC-V core is presented. The paper offers a guide on the test-planning used and details of the flow architecture, showing how to integrate the Universal Verification Methodology with the required, reference models, while implementing key futures in standard verification environments, such as testing regressions and code and structural coverage. The designed flow is compact yet efficient, making it affordable for small design teams, without requiring extra investment other than the already necessary licenses for RTL synthesis and the eventual fabrication of the chip.
| 2020 | |
| Agencia Nacional de Investigación e Innovación | |
|
Functional verification RISC-V 321 UVM System Verilog EDA tools Architecture Test generation Compiler Processor Simulation Coverage Regression Reference model |
|
| Inglés | |
| Universidad Católica del Uruguay | |
| LIBERI | |
| https://hdl.handle.net/10895/1549 | |
| Acceso abierto | |
| Licencia Creative Commons Atribución – No Comercial – Sin Derivadas (CC BY-NC-ND 4.0) |
| _version_ | 1815178684375498752 |
|---|---|
| author | Molina Robles, Roberto |
| author2 | Solera Bolanos, Edgar García Ramírez, Ronny Chacón Rodríguez, Alfonso Rimolo Donadio, Renato Arnaud Maceira, Alfredo |
| author2_role | author author author author author |
| author_facet | Molina Robles, Roberto Solera Bolanos, Edgar García Ramírez, Ronny Chacón Rodríguez, Alfonso Rimolo Donadio, Renato Arnaud Maceira, Alfredo |
| author_role | author |
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| bitstream.checksumAlgorithm.fl_str_mv | MD5 MD5 MD5 MD5 |
| bitstream.url.fl_str_mv | http://liberi.ucu.edu.uy/xmlui/bitstream/10895/1549/1/A_compact_functional_verification_flow_for_a_RISC-V_32I_based_core.pdf http://liberi.ucu.edu.uy/xmlui/bitstream/10895/1549/2/license.txt http://liberi.ucu.edu.uy/xmlui/bitstream/10895/1549/3/A_compact_functional_verification_flow_for_a_RISC-V_32I_based_core.pdf.txt http://liberi.ucu.edu.uy/xmlui/bitstream/10895/1549/4/A_compact_functional_verification_flow_for_a_RISC-V_32I_based_core.pdf.jpg |
| collection | LIBERI |
| dc.creator.none.fl_str_mv | Molina Robles, Roberto Solera Bolanos, Edgar García Ramírez, Ronny Chacón Rodríguez, Alfonso Rimolo Donadio, Renato Arnaud Maceira, Alfredo |
| dc.date.accessioned.none.fl_str_mv | 2021-10-21T18:07:06Z |
| dc.date.available.none.fl_str_mv | 2021-10-21T18:07:06Z |
| dc.date.issued.none.fl_str_mv | 2020 |
| dc.description.abstract.none.fl_txt_mv | The structure of a functional verification flow used for the design of a RISC-V core is presented. The paper offers a guide on the test-planning used and details of the flow architecture, showing how to integrate the Universal Verification Methodology with the required, reference models, while implementing key futures in standard verification environments, such as testing regressions and code and structural coverage. The designed flow is compact yet efficient, making it affordable for small design teams, without requiring extra investment other than the already necessary licenses for RTL synthesis and the eventual fabrication of the chip. |
| dc.description.sponsorship.none.fl_txt_mv | Agencia Nacional de Investigación e Innovación |
| dc.format.mimetype.none.fl_str_mv | application/pdf |
| dc.identifier.uri.none.fl_str_mv | https://hdl.handle.net/10895/1549 |
| dc.language.iso.none.fl_str_mv | eng |
| dc.publisher.es.fl_str_mv | IEEE |
| dc.relation.ispartof.none.fl_str_mv | 3rd Conference on PhD Research in Microelectronics and Electronics, 2020 |
| dc.rights.license.none.fl_str_mv | Licencia Creative Commons Atribución – No Comercial – Sin Derivadas (CC BY-NC-ND 4.0) |
| dc.rights.none.fl_str_mv | info:eu-repo/semantics/openAccess |
| dc.source.none.fl_str_mv | reponame:LIBERI instname:Universidad Católica del Uruguay instacron:Universidad Católica del Uruguay |
| dc.subject.es.fl_str_mv | Functional verification RISC-V 321 UVM System Verilog EDA tools Architecture Test generation Compiler Processor Simulation Coverage Regression Reference model |
| dc.title.none.fl_str_mv | A compact functional verification flow for a RISC-V 321 based core |
| dc.type.es.fl_str_mv | Artículo |
| dc.type.none.fl_str_mv | info:eu-repo/semantics/article |
| dc.type.version.none.fl_str_mv | info:eu-repo/semantics/publishedVersion |
| description | The structure of a functional verification flow used for the design of a RISC-V core is presented. The paper offers a guide on the test-planning used and details of the flow architecture, showing how to integrate the Universal Verification Methodology with the required, reference models, while implementing key futures in standard verification environments, such as testing regressions and code and structural coverage. The designed flow is compact yet efficient, making it affordable for small design teams, without requiring extra investment other than the already necessary licenses for RTL synthesis and the eventual fabrication of the chip. |
| eu_rights_str_mv | openAccess |
| format | article |
| id | LIBERI_e6e6758ef030fd63a0e245891f9cfb5c |
| instacron_str | Universidad Católica del Uruguay |
| institution | Universidad Católica del Uruguay |
| instname_str | Universidad Católica del Uruguay |
| language | eng |
| network_acronym_str | LIBERI |
| network_name_str | LIBERI |
| oai_identifier_str | oai:liberi.ucu.edu.uy:10895/1549 |
| publishDate | 2020 |
| reponame_str | LIBERI |
| repository.mail.fl_str_mv | franco.pertusso@ucu.edu.uy |
| repository.name.fl_str_mv | LIBERI - Universidad Católica del Uruguay |
| repository_id_str | 10342 |
| rights_invalid_str_mv | Licencia Creative Commons Atribución – No Comercial – Sin Derivadas (CC BY-NC-ND 4.0) |
| spelling | Licencia Creative Commons Atribución – No Comercial – Sin Derivadas (CC BY-NC-ND 4.0)info:eu-repo/semantics/openAccess2021-10-21T18:07:06Z2021-10-21T18:07:06Z2020https://hdl.handle.net/10895/1549The structure of a functional verification flow used for the design of a RISC-V core is presented. The paper offers a guide on the test-planning used and details of the flow architecture, showing how to integrate the Universal Verification Methodology with the required, reference models, while implementing key futures in standard verification environments, such as testing regressions and code and structural coverage. The designed flow is compact yet efficient, making it affordable for small design teams, without requiring extra investment other than the already necessary licenses for RTL synthesis and the eventual fabrication of the chip.Agencia Nacional de Investigación e Innovaciónapplication/pdfIEEE3rd Conference on PhD Research in Microelectronics and Electronics, 2020Functional verificationRISC-V 321UVMSystem VerilogEDA toolsArchitectureTest generationCompilerProcessorSimulationCoverageRegressionReference modelA compact functional verification flow for a RISC-V 321 based coreArtículoinfo:eu-repo/semantics/articleinfo:eu-repo/semantics/publishedVersionreponame:LIBERIinstname:Universidad Católica del Uruguayinstacron:Universidad Católica del UruguayMolina Robles, RobertoSolera Bolanos, EdgarGarcía Ramírez, RonnyChacón Rodríguez, AlfonsoRimolo Donadio, RenatoArnaud Maceira, AlfredoengORIGINALA_compact_functional_verification_flow_for_a_RISC-V_32I_based_core.pdfA_compact_functional_verification_flow_for_a_RISC-V_32I_based_core.pdfapplication/pdf316315http://liberi.ucu.edu.uy/xmlui/bitstream/10895/1549/1/A_compact_functional_verification_flow_for_a_RISC-V_32I_based_core.pdf302b22ba4ba6cdfdeddb6456358f81e8MD51LICENSElicense.txtlicense.txttext/plain; charset=utf-81748http://liberi.ucu.edu.uy/xmlui/bitstream/10895/1549/2/license.txt8a4605be74aa9ea9d79846c1fba20a33MD52TEXTA_compact_functional_verification_flow_for_a_RISC-V_32I_based_core.pdf.txtA_compact_functional_verification_flow_for_a_RISC-V_32I_based_core.pdf.txtExtracted texttext/plain21255http://liberi.ucu.edu.uy/xmlui/bitstream/10895/1549/3/A_compact_functional_verification_flow_for_a_RISC-V_32I_based_core.pdf.txt6a2ca27d1d821e1b52d0d6d1ec7600c9MD53THUMBNAILA_compact_functional_verification_flow_for_a_RISC-V_32I_based_core.pdf.jpgA_compact_functional_verification_flow_for_a_RISC-V_32I_based_core.pdf.jpgGenerated Thumbnailimage/jpeg7793http://liberi.ucu.edu.uy/xmlui/bitstream/10895/1549/4/A_compact_functional_verification_flow_for_a_RISC-V_32I_based_core.pdf.jpg9d57a11b457a81422bea9a059728ee10MD5410895/15492021-11-10 17:54:25.514oai:liberi.ucu.edu.uy:10895/1549Tk9URTogUExBQ0UgWU9VUiBPV04gTElDRU5TRSBIRVJFClRoaXMgc2FtcGxlIGxpY2Vuc2UgaXMgcHJvdmlkZWQgZm9yIGluZm9ybWF0aW9uYWwgcHVycG9zZXMgb25seS4KCk5PTi1FWENMVVNJVkUgRElTVFJJQlVUSU9OIExJQ0VOU0UKCkJ5IHNpZ25pbmcgYW5kIHN1Ym1pdHRpbmcgdGhpcyBsaWNlbnNlLCB5b3UgKHRoZSBhdXRob3Iocykgb3IgY29weXJpZ2h0Cm93bmVyKSBncmFudHMgdG8gRFNwYWNlIFVuaXZlcnNpdHkgKERTVSkgdGhlIG5vbi1leGNsdXNpdmUgcmlnaHQgdG8gcmVwcm9kdWNlLAp0cmFuc2xhdGUgKGFzIGRlZmluZWQgYmVsb3cpLCBhbmQvb3IgZGlzdHJpYnV0ZSB5b3VyIHN1Ym1pc3Npb24gKGluY2x1ZGluZwp0aGUgYWJzdHJhY3QpIHdvcmxkd2lkZSBpbiBwcmludCBhbmQgZWxlY3Ryb25pYyBmb3JtYXQgYW5kIGluIGFueSBtZWRpdW0sCmluY2x1ZGluZyBidXQgbm90IGxpbWl0ZWQgdG8gYXVkaW8gb3IgdmlkZW8uCgpZb3UgYWdyZWUgdGhhdCBEU1UgbWF5LCB3aXRob3V0IGNoYW5naW5nIHRoZSBjb250ZW50LCB0cmFuc2xhdGUgdGhlCnN1Ym1pc3Npb24gdG8gYW55IG1lZGl1bSBvciBmb3JtYXQgZm9yIHRoZSBwdXJwb3NlIG9mIHByZXNlcnZhdGlvbi4KCllvdSBhbHNvIGFncmVlIHRoYXQgRFNVIG1heSBrZWVwIG1vcmUgdGhhbiBvbmUgY29weSBvZiB0aGlzIHN1Ym1pc3Npb24gZm9yCnB1cnBvc2VzIG9mIHNlY3VyaXR5LCBiYWNrLXVwIGFuZCBwcmVzZXJ2YXRpb24uCgpZb3UgcmVwcmVzZW50IHRoYXQgdGhlIHN1Ym1pc3Npb24gaXMgeW91ciBvcmlnaW5hbCB3b3JrLCBhbmQgdGhhdCB5b3UgaGF2ZQp0aGUgcmlnaHQgdG8gZ3JhbnQgdGhlIHJpZ2h0cyBjb250YWluZWQgaW4gdGhpcyBsaWNlbnNlLiBZb3UgYWxzbyByZXByZXNlbnQKdGhhdCB5b3VyIHN1Ym1pc3Npb24gZG9lcyBub3QsIHRvIHRoZSBiZXN0IG9mIHlvdXIga25vd2xlZGdlLCBpbmZyaW5nZSB1cG9uCmFueW9uZSdzIGNvcHlyaWdodC4KCklmIHRoZSBzdWJtaXNzaW9uIGNvbnRhaW5zIG1hdGVyaWFsIGZvciB3aGljaCB5b3UgZG8gbm90IGhvbGQgY29weXJpZ2h0LAp5b3UgcmVwcmVzZW50IHRoYXQgeW91IGhhdmUgb2J0YWluZWQgdGhlIHVucmVzdHJpY3RlZCBwZXJtaXNzaW9uIG9mIHRoZQpjb3B5cmlnaHQgb3duZXIgdG8gZ3JhbnQgRFNVIHRoZSByaWdodHMgcmVxdWlyZWQgYnkgdGhpcyBsaWNlbnNlLCBhbmQgdGhhdApzdWNoIHRoaXJkLXBhcnR5IG93bmVkIG1hdGVyaWFsIGlzIGNsZWFybHkgaWRlbnRpZmllZCBhbmQgYWNrbm93bGVkZ2VkCndpdGhpbiB0aGUgdGV4dCBvciBjb250ZW50IG9mIHRoZSBzdWJtaXNzaW9uLgoKSUYgVEhFIFNVQk1JU1NJT04gSVMgQkFTRUQgVVBPTiBXT1JLIFRIQVQgSEFTIEJFRU4gU1BPTlNPUkVEIE9SIFNVUFBPUlRFRApCWSBBTiBBR0VOQ1kgT1IgT1JHQU5JWkFUSU9OIE9USEVSIFRIQU4gRFNVLCBZT1UgUkVQUkVTRU5UIFRIQVQgWU9VIEhBVkUKRlVMRklMTEVEIEFOWSBSSUdIVCBPRiBSRVZJRVcgT1IgT1RIRVIgT0JMSUdBVElPTlMgUkVRVUlSRUQgQlkgU1VDSApDT05UUkFDVCBPUiBBR1JFRU1FTlQuCgpEU1Ugd2lsbCBjbGVhcmx5IGlkZW50aWZ5IHlvdXIgbmFtZShzKSBhcyB0aGUgYXV0aG9yKHMpIG9yIG93bmVyKHMpIG9mIHRoZQpzdWJtaXNzaW9uLCBhbmQgd2lsbCBub3QgbWFrZSBhbnkgYWx0ZXJhdGlvbiwgb3RoZXIgdGhhbiBhcyBhbGxvd2VkIGJ5IHRoaXMKbGljZW5zZSwgdG8geW91ciBzdWJtaXNzaW9uLgo=Universidadhttps://www.ucu.edu.uy/https://liberi.ucu.edu.uy/oai/requestfranco.pertusso@ucu.edu.uyUruguayopendoar:103422021-11-10T20:54:25LIBERI - Universidad Católica del Uruguayfalse |
| spellingShingle | A compact functional verification flow for a RISC-V 321 based core Molina Robles, Roberto Functional verification RISC-V 321 UVM System Verilog EDA tools Architecture Test generation Compiler Processor Simulation Coverage Regression Reference model |
| status_str | publishedVersion |
| title | A compact functional verification flow for a RISC-V 321 based core |
| title_full | A compact functional verification flow for a RISC-V 321 based core |
| title_fullStr | A compact functional verification flow for a RISC-V 321 based core |
| title_full_unstemmed | A compact functional verification flow for a RISC-V 321 based core |
| title_short | A compact functional verification flow for a RISC-V 321 based core |
| title_sort | A compact functional verification flow for a RISC-V 321 based core |
| topic | Functional verification RISC-V 321 UVM System Verilog EDA tools Architecture Test generation Compiler Processor Simulation Coverage Regression Reference model |
| url | https://hdl.handle.net/10895/1549 |
