Siwa: a RISC-V RV32I based micro-controller for implantable medical applications

García Ramírez, Ronny - Chacón Rodríguez, Alfonso - Castro González, Reinaldo - Arnaud Maceira, Alfredo - Miguez de Mori, Matías Rafael - Gak Szollosy, Joel - Molina Robles, Roberto - Madrigal Boza, Gabriel - Oviedo Hernández, Marco - Solera Bolanos, Edgar - Salazar Sibaja, Diego - Sánchez Jiménez, Dayhana - Fonseca Rodríguez, Melissa - Arrieta Solorzano, Johan - Rimolo Donadio, Renato

Resumen:

The design of Siwa1, a compact low power custom system on chip (SoC), targeted for implantable/wearable applications, is reported in this paper. Siwa is based on a RISC-V RV32I architecture. It has a centrally controlled non-pipelined structure, and it includes a control interface for an integrated sensing and stimulation device for biological tissues as well as standard communication interfaces. Siwa was developed from scratch using System Verilog, and implemented in a 180nm CMOS technology; Siwa includes a latch based register file c apable to read and write in one clock cycle with an area 30% smaller and a power consumption 25% lower with respect to an equivalent flip flop implementation; also, it has an estimated average power consumption of 70μW (48pJ/cycle) which is comparable to other micro-controllers commonly used in IMD applications.


Detalles Bibliográficos
2020
Agencia Nacional de Investigación e Innovación
IMD
RISC-V
Micro-architecture
System on chip
Digital VLSI
Inglés
Universidad Católica del Uruguay
LIBERI
https://hdl.handle.net/10895/1557
Acceso abierto
Licencia Creative Commons Atribución – No Comercial – Sin Derivadas (CC BY-NC-ND 4.0)
Resumen:
Sumario:The design of Siwa1, a compact low power custom system on chip (SoC), targeted for implantable/wearable applications, is reported in this paper. Siwa is based on a RISC-V RV32I architecture. It has a centrally controlled non-pipelined structure, and it includes a control interface for an integrated sensing and stimulation device for biological tissues as well as standard communication interfaces. Siwa was developed from scratch using System Verilog, and implemented in a 180nm CMOS technology; Siwa includes a latch based register file c apable to read and write in one clock cycle with an area 30% smaller and a power consumption 25% lower with respect to an equivalent flip flop implementation; also, it has an estimated average power consumption of 70μW (48pJ/cycle) which is comparable to other micro-controllers commonly used in IMD applications.

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