High CMRR power efficient neural recording amplifier architecture
Resumen:
This work presents an architecture of neural record- ing amplifier based on a modified differential difference amplifier (DDA). The proposed circuit improves the performance with respect to capacitive feedback neural amplifiers and standard DDA based amplifiers by taking advantage of the high CMRR achievable in a DDA without jeopardizing the power con- sumption. In addition a novel technique for rejecting the DC component at the output of the amplifier and fixing the low cut-off frequency is described. The expected performance of the circuit is checked by Monte Carlo simulation, achieving 48dB gain in a 250Hz-8kHz bandwidth, with higher than 107dB CMRR (@5kHZ), 2.4Vrms input noise and 4.2 noise efficiency factor at a total current consumption of 16.5A from a 3.3V power supply in a 0.5m CMOS technology
| 2011 | |
| Electrónica | |
| Inglés | |
| Universidad de la República | |
| COLIBRI | |
| https://hdl.handle.net/20.500.12008/41093 | |
| Acceso abierto | |
| Licencia Creative Commons Atribución - No Comercial - Sin Derivadas (CC - By-NC-ND 4.0) |
| _version_ | 1807522936667504640 |
|---|---|
| author | Castro Lisboa, Pablo |
| author2 | Silveira, Fernando |
| author2_role | author |
| author_facet | Castro Lisboa, Pablo Silveira, Fernando |
| author_role | author |
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| collection | COLIBRI |
| dc.creator.none.fl_str_mv | Castro Lisboa, Pablo Silveira, Fernando |
| dc.date.accessioned.none.fl_str_mv | 2023-11-14T17:04:14Z |
| dc.date.available.none.fl_str_mv | 2023-11-14T17:04:14Z |
| dc.date.issued.es.fl_str_mv | 2011 |
| dc.date.submitted.es.fl_str_mv | 20231114 |
| dc.description.abstract.none.fl_txt_mv | This work presents an architecture of neural record- ing amplifier based on a modified differential difference amplifier (DDA). The proposed circuit improves the performance with respect to capacitive feedback neural amplifiers and standard DDA based amplifiers by taking advantage of the high CMRR achievable in a DDA without jeopardizing the power con- sumption. In addition a novel technique for rejecting the DC component at the output of the amplifier and fixing the low cut-off frequency is described. The expected performance of the circuit is checked by Monte Carlo simulation, achieving 48dB gain in a 250Hz-8kHz bandwidth, with higher than 107dB CMRR (@5kHZ), 2.4Vrms input noise and 4.2 noise efficiency factor at a total current consumption of 16.5A from a 3.3V power supply in a 0.5m CMOS technology |
| dc.description.es.fl_txt_mv | Trabajo presentado al 2011 IEEE International Symposium of Circuits and Systems (ISCAS), Rio de Janeiro, Brazil. |
| dc.identifier.citation.es.fl_str_mv | Castro, P, Silveira, F. "High CMRR power efficient neural recording amplifier architecture" Publicado en: Proceedings of the IEEE International Symposium of Circuits and Systems (ISCAS), Rio de Janeiro, Brazil, 2011, pp. 1700-1703, doi: 10.1109/ISCAS.2011.5937909. |
| dc.identifier.uri.none.fl_str_mv | https://hdl.handle.net/20.500.12008/41093 |
| dc.language.iso.none.fl_str_mv | en eng |
| dc.rights.license.none.fl_str_mv | Licencia Creative Commons Atribución - No Comercial - Sin Derivadas (CC - By-NC-ND 4.0) |
| dc.rights.none.fl_str_mv | info:eu-repo/semantics/openAccess |
| dc.source.none.fl_str_mv | reponame:COLIBRI instname:Universidad de la República instacron:Universidad de la República |
| dc.subject.other.es.fl_str_mv | Electrónica |
| dc.title.none.fl_str_mv | High CMRR power efficient neural recording amplifier architecture |
| dc.type.es.fl_str_mv | Ponencia |
| dc.type.none.fl_str_mv | info:eu-repo/semantics/conferenceObject |
| dc.type.version.none.fl_str_mv | info:eu-repo/semantics/publishedVersion |
| description | Trabajo presentado al 2011 IEEE International Symposium of Circuits and Systems (ISCAS), Rio de Janeiro, Brazil. |
| eu_rights_str_mv | openAccess |
| format | conferenceObject |
| id | COLIBRI_f89c167ec5af64ba2cb9a2dab9241df4 |
| identifier_str_mv | Castro, P, Silveira, F. "High CMRR power efficient neural recording amplifier architecture" Publicado en: Proceedings of the IEEE International Symposium of Circuits and Systems (ISCAS), Rio de Janeiro, Brazil, 2011, pp. 1700-1703, doi: 10.1109/ISCAS.2011.5937909. |
| instacron_str | Universidad de la República |
| institution | Universidad de la República |
| instname_str | Universidad de la República |
| language | eng |
| language_invalid_str_mv | en |
| network_acronym_str | COLIBRI |
| network_name_str | COLIBRI |
| oai_identifier_str | oai:colibri.udelar.edu.uy:20.500.12008/41093 |
| publishDate | 2011 |
| reponame_str | COLIBRI |
| repository.mail.fl_str_mv | mabel.seroubian@seciu.edu.uy |
| repository.name.fl_str_mv | COLIBRI - Universidad de la República |
| repository_id_str | 4771 |
| rights_invalid_str_mv | Licencia Creative Commons Atribución - No Comercial - Sin Derivadas (CC - By-NC-ND 4.0) |
| spelling | 2023-11-14T17:04:14Z2023-11-14T17:04:14Z201120231114Castro, P, Silveira, F. "High CMRR power efficient neural recording amplifier architecture" Publicado en: Proceedings of the IEEE International Symposium of Circuits and Systems (ISCAS), Rio de Janeiro, Brazil, 2011, pp. 1700-1703, doi: 10.1109/ISCAS.2011.5937909.https://hdl.handle.net/20.500.12008/41093Trabajo presentado al 2011 IEEE International Symposium of Circuits and Systems (ISCAS), Rio de Janeiro, Brazil.This work presents an architecture of neural record- ing amplifier based on a modified differential difference amplifier (DDA). The proposed circuit improves the performance with respect to capacitive feedback neural amplifiers and standard DDA based amplifiers by taking advantage of the high CMRR achievable in a DDA without jeopardizing the power con- sumption. In addition a novel technique for rejecting the DC component at the output of the amplifier and fixing the low cut-off frequency is described. The expected performance of the circuit is checked by Monte Carlo simulation, achieving 48dB gain in a 250Hz-8kHz bandwidth, with higher than 107dB CMRR (@5kHZ), 2.4Vrms input noise and 4.2 noise efficiency factor at a total current consumption of 16.5A from a 3.3V power supply in a 0.5m CMOS technologyMade available in DSpace on 2023-11-14T17:04:14Z (GMT). No. of bitstreams: 5 CS11.pdf: 267985 bytes, checksum: 97cc71266b2f42178f29df6374aa2cc4 (MD5) license_text: 21936 bytes, checksum: 9833653f73f7853880c94a6fead477b1 (MD5) license_url: 49 bytes, checksum: 4afdbb8c545fd630ea7db775da747b2f (MD5) license_rdf: 23148 bytes, checksum: 9da0b6dfac957114c6a7714714b86306 (MD5) license.txt: 4194 bytes, checksum: 7f2e2c17ef6585de66da58d1bfa8b5e1 (MD5) Previous issue date: 2011enengLas obras depositadas en el Repositorio se rigen por la Ordenanza de los Derechos de la Propiedad Intelectual de la Universidad De La República. (Res. Nº 91 de C.D.C. de 8/III/1994 – D.O. 7/IV/1994) y por la Ordenanza del Repositorio Abierto de la Universidad de la República (Res. Nº 16 de C.D.C. de 07/10/2014)info:eu-repo/semantics/openAccessLicencia Creative Commons Atribución - No Comercial - Sin Derivadas (CC - By-NC-ND 4.0)ElectrónicaHigh CMRR power efficient neural recording amplifier architecturePonenciainfo:eu-repo/semantics/conferenceObjectinfo:eu-repo/semantics/publishedVersionreponame:COLIBRIinstname:Universidad de la Repúblicainstacron:Universidad de la RepúblicaCastro Lisboa, PabloSilveira, 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- Universidad de la Repúblicafalse |
| spellingShingle | High CMRR power efficient neural recording amplifier architecture Castro Lisboa, Pablo Electrónica |
| status_str | publishedVersion |
| title | High CMRR power efficient neural recording amplifier architecture |
| title_full | High CMRR power efficient neural recording amplifier architecture |
| title_fullStr | High CMRR power efficient neural recording amplifier architecture |
| title_full_unstemmed | High CMRR power efficient neural recording amplifier architecture |
| title_short | High CMRR power efficient neural recording amplifier architecture |
| title_sort | High CMRR power efficient neural recording amplifier architecture |
| topic | Electrónica |
| url | https://hdl.handle.net/20.500.12008/41093 |
