Capacitances in compact 7-Parameter model for analog design in nanoscale process
Resumen:
Lately efforts have been made to have compact models for nanoscale processes with a small number of parameters. These models consider one to four extra parameters in addition to the three basic parameters of the long-channel transistor compact models, which are the slope factor, the equilibrium threshold voltage and the normalization current. An acceptable accuracy of the dc characteristics and the small-signal parameters is obtained through these models. This work analyzes whether it is possible to obtain an adequate model of the intrinsic part of the capacitances by means of these models and parameters, while proposing a simple method to account for the extrinsic part of the capacitances. The proposed method, together with the model, is tested for minimum-length transistors in an FD-SOI 28 nm process and applied to the design of a low-voltage LC oscillator. The results obtained by these means are compared with the results of a look-up table approach and with simulation results, showing a reasonable agreement.
| 2023 | |
| Los autores desean agradecer a CSIC de Universidad de la República de Uruguay | |
|
Analog design methodology MOS capacitance model Nanoscale process Low-voltage design Compact model |
|
| Inglés | |
| Universidad de la República | |
| COLIBRI | |
| https://hdl.handle.net/20.500.12008/54674 | |
| Acceso abierto | |
| Licencia Creative Commons Atribución - No Comercial - Sin Derivadas (CC - By-NC-ND 4.0) |
| _version_ | 1875692335847702528 |
|---|---|
| author | Siniscalchi, Mariana |
| author2 | Gammarano, Nicolás Silveira, Fernando |
| author2_role | author author |
| author_facet | Siniscalchi, Mariana Gammarano, Nicolás Silveira, Fernando |
| author_role | author |
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| collection | COLIBRI |
| dc.contributor.filiacion.none.fl_str_mv | Siniscalchi Mariana, Universidad de la República (Uruguay). Facultad de Ingeniería. Gammarano Nicolás, Universidad de la República (Uruguay). Facultad de Ingeniería. Silveira Fernando, Universidad de la República (Uruguay). Facultad de Ingeniería. |
| dc.creator.none.fl_str_mv | Siniscalchi, Mariana Gammarano, Nicolás Silveira, Fernando |
| dc.date.accessioned.none.fl_str_mv | 2026-04-29T13:41:39Z |
| dc.date.available.none.fl_str_mv | 2026-04-29T13:41:39Z |
| dc.date.issued.none.fl_str_mv | 2023 |
| dc.description.abstract.none.fl_txt_mv | Lately efforts have been made to have compact models for nanoscale processes with a small number of parameters. These models consider one to four extra parameters in addition to the three basic parameters of the long-channel transistor compact models, which are the slope factor, the equilibrium threshold voltage and the normalization current. An acceptable accuracy of the dc characteristics and the small-signal parameters is obtained through these models. This work analyzes whether it is possible to obtain an adequate model of the intrinsic part of the capacitances by means of these models and parameters, while proposing a simple method to account for the extrinsic part of the capacitances. The proposed method, together with the model, is tested for minimum-length transistors in an FD-SOI 28 nm process and applied to the design of a low-voltage LC oscillator. The results obtained by these means are compared with the results of a look-up table approach and with simulation results, showing a reasonable agreement. |
| dc.description.sponsorship.none.fl_txt_mv | Los autores desean agradecer a CSIC de Universidad de la República de Uruguay |
| dc.format.extent.es.fl_str_mv | 5 p. |
| dc.format.mimetype.es.fl_str_mv | application/pdf |
| dc.identifier.citation.es.fl_str_mv | Siniscalchi, M., Gammarano, N. y Silveira, F. Capacitances in compact 7-Parameter model for analog design in nanoscale process [en línea]. EN: 2023 IEEE International Symposium on Circuits and Systems (ISCAS), Monterey, CA, USA, 21-25 may. 2023, pp. 1-5. |
| dc.identifier.uri.none.fl_str_mv | https://hdl.handle.net/20.500.12008/54674 |
| dc.language.iso.none.fl_str_mv | en eng |
| dc.relation.none.fl_str_mv | 2023 IEEE International Symposium on Circuits and Systems (ISCAS), Monterey, CA, USA, 21-25 may. 2023, pp. 1-5. |
| dc.rights.license.none.fl_str_mv | Licencia Creative Commons Atribución - No Comercial - Sin Derivadas (CC - By-NC-ND 4.0) |
| dc.rights.none.fl_str_mv | info:eu-repo/semantics/openAccess |
| dc.source.none.fl_str_mv | reponame:COLIBRI instname:Universidad de la República instacron:Universidad de la República |
| dc.subject.es.fl_str_mv | Analog design methodology MOS capacitance model Nanoscale process Low-voltage design Compact model |
| dc.title.none.fl_str_mv | Capacitances in compact 7-Parameter model for analog design in nanoscale process |
| dc.type.es.fl_str_mv | Ponencia |
| dc.type.none.fl_str_mv | info:eu-repo/semantics/conferenceObject |
| dc.type.version.none.fl_str_mv | info:eu-repo/semantics/publishedVersion |
| description | Lately efforts have been made to have compact models for nanoscale processes with a small number of parameters. These models consider one to four extra parameters in addition to the three basic parameters of the long-channel transistor compact models, which are the slope factor, the equilibrium threshold voltage and the normalization current. An acceptable accuracy of the dc characteristics and the small-signal parameters is obtained through these models. This work analyzes whether it is possible to obtain an adequate model of the intrinsic part of the capacitances by means of these models and parameters, while proposing a simple method to account for the extrinsic part of the capacitances. The proposed method, together with the model, is tested for minimum-length transistors in an FD-SOI 28 nm process and applied to the design of a low-voltage LC oscillator. The results obtained by these means are compared with the results of a look-up table approach and with simulation results, showing a reasonable agreement. |
| eu_rights_str_mv | openAccess |
| format | conferenceObject |
| id | COLIBRI_e295147a1f8ba5789301c516c49beafe |
| identifier_str_mv | Siniscalchi, M., Gammarano, N. y Silveira, F. Capacitances in compact 7-Parameter model for analog design in nanoscale process [en línea]. EN: 2023 IEEE International Symposium on Circuits and Systems (ISCAS), Monterey, CA, USA, 21-25 may. 2023, pp. 1-5. |
| instacron_str | Universidad de la República |
| institution | Universidad de la República |
| instname_str | Universidad de la República |
| language | eng |
| language_invalid_str_mv | en |
| network_acronym_str | COLIBRI |
| network_name_str | COLIBRI |
| oai_identifier_str | oai:colibri.udelar.edu.uy:20.500.12008/54674 |
| publishDate | 2023 |
| reponame_str | COLIBRI |
| repository.mail.fl_str_mv | karina.camps@seciu.edu.uy |
| repository.name.fl_str_mv | COLIBRI - Universidad de la República |
| repository_id_str | 4771 |
| rights_invalid_str_mv | Licencia Creative Commons Atribución - No Comercial - Sin Derivadas (CC - By-NC-ND 4.0) |
| spelling | Siniscalchi Mariana, Universidad de la República (Uruguay). Facultad de Ingeniería.Gammarano Nicolás, Universidad de la República (Uruguay). Facultad de Ingeniería.Silveira Fernando, Universidad de la República (Uruguay). Facultad de Ingeniería.2026-04-29T13:41:39Z2026-04-29T13:41:39Z2023Siniscalchi, M., Gammarano, N. y Silveira, F. Capacitances in compact 7-Parameter model for analog design in nanoscale process [en línea]. EN: 2023 IEEE International Symposium on Circuits and Systems (ISCAS), Monterey, CA, USA, 21-25 may. 2023, pp. 1-5.https://hdl.handle.net/20.500.12008/54674Lately efforts have been made to have compact models for nanoscale processes with a small number of parameters. These models consider one to four extra parameters in addition to the three basic parameters of the long-channel transistor compact models, which are the slope factor, the equilibrium threshold voltage and the normalization current. An acceptable accuracy of the dc characteristics and the small-signal parameters is obtained through these models. This work analyzes whether it is possible to obtain an adequate model of the intrinsic part of the capacitances by means of these models and parameters, while proposing a simple method to account for the extrinsic part of the capacitances. The proposed method, together with the model, is tested for minimum-length transistors in an FD-SOI 28 nm process and applied to the design of a low-voltage LC oscillator. The results obtained by these means are compared with the results of a look-up table approach and with simulation results, showing a reasonable agreement.Submitted by Ribeiro Jorge (jribeiro@fing.edu.uy) on 2026-04-28T21:35:36Z No. of bitstreams: 2 license_rdf: 27293 bytes, checksum: d62648cf14c1e37917d392ac87012955 (MD5) SGS23.pdf: 373044 bytes, checksum: 4e6cecbb49a2a360e5d13e8cfdf90f9c (MD5)Approved for entry into archive by Machado Jimena (jmachado@fing.edu.uy) on 2026-04-29T13:08:01Z (GMT) No. of bitstreams: 2 license_rdf: 27293 bytes, checksum: d62648cf14c1e37917d392ac87012955 (MD5) SGS23.pdf: 373044 bytes, checksum: 4e6cecbb49a2a360e5d13e8cfdf90f9c (MD5)Made available in DSpace by Luna Fabiana (fabiana.luna@seciu.edu.uy) on 2026-04-29T13:41:39Z (GMT). No. of bitstreams: 2 license_rdf: 27293 bytes, checksum: d62648cf14c1e37917d392ac87012955 (MD5) SGS23.pdf: 373044 bytes, checksum: 4e6cecbb49a2a360e5d13e8cfdf90f9c (MD5) Previous issue date: 2023Los autores desean agradecer a CSIC de Universidad de la República de Uruguay5 p.application/pdfeneng2023 IEEE International Symposium on Circuits and Systems (ISCAS), Monterey, CA, USA, 21-25 may. 2023, pp. 1-5.Las obras depositadas en el Repositorio se rigen por la Ordenanza de los Derechos de la Propiedad Intelectual de la Universidad de la República.(Res. Nº 91 de C.D.C. de 8/III/1994 – D.O. 7/IV/1994) y por la Ordenanza del Repositorio Abierto de la Universidad de la República (Res. Nº 16 de C.D.C. de 07/10/2014)info:eu-repo/semantics/openAccessLicencia Creative Commons Atribución - No Comercial - Sin Derivadas (CC - By-NC-ND 4.0)Analog design methodologyMOS capacitance modelNanoscale processLow-voltage designCompact modelCapacitances in compact 7-Parameter model for analog design in nanoscale processPonenciainfo:eu-repo/semantics/conferenceObjectinfo:eu-repo/semantics/publishedVersionreponame:COLIBRIinstname:Universidad de la Repúblicainstacron:Universidad de la RepúblicaSiniscalchi, MarianaGammarano, NicolásSilveira, FernandoElectrónicaMicroelectrónicaLICENSElicense.txtlicense.txttext/plain; charset=utf-84267http://localhost:8080/xmlui/bitstream/20.500.12008/54674/5/license.txt6429389a7df7277b72b7924fdc7d47a9MD55CC-LICENSElicense_urllicense_urltext/plain; charset=utf-850http://localhost:8080/xmlui/bitstream/20.500.12008/54674/2/license_urla006180e3f5b2ad0b88185d14284c0e0MD52license_textlicense_texttext/html; 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- Universidad de la Repúblicafalse |
| spellingShingle | Capacitances in compact 7-Parameter model for analog design in nanoscale process Siniscalchi, Mariana Analog design methodology MOS capacitance model Nanoscale process Low-voltage design Compact model |
| status_str | publishedVersion |
| title | Capacitances in compact 7-Parameter model for analog design in nanoscale process |
| title_full | Capacitances in compact 7-Parameter model for analog design in nanoscale process |
| title_fullStr | Capacitances in compact 7-Parameter model for analog design in nanoscale process |
| title_full_unstemmed | Capacitances in compact 7-Parameter model for analog design in nanoscale process |
| title_short | Capacitances in compact 7-Parameter model for analog design in nanoscale process |
| title_sort | Capacitances in compact 7-Parameter model for analog design in nanoscale process |
| topic | Analog design methodology MOS capacitance model Nanoscale process Low-voltage design Compact model |
| url | https://hdl.handle.net/20.500.12008/54674 |