A design procedure that determines the combination of linear settling time (i.e. gain bandwidth) and slew rate that minimizes an amplifier total power consumption, while complying with a given total settling time specification, is presented. The method is presented for a Miller OTA, but can be generalized to other architectures. The proposed approach also provides the optimum combination of the g/sub m//I/sub D/ ratios of the input and output transistors and the transistor design corresponding to this optimum of power consumption. It is shown that the application of fixed "rules of thumb" criteria for the assignment of the allowable linear settling and slewing periods leads to highly increased consumption. The method is based on a simple, design oriented model of the settling behavior that is also described in this paper. This model is checked against experimental results and the design procedure results are verified with SPICE simulations