Design method for an ultra low power, low offset, symmetric OTA
Resumen:
A design method for ultra low power, low offset, symmetric OTAs is presented. The method is based on the gm/ID methodology and uses a model of MOS transistor valid in all the regions of operation which assures that the optimal operating point is chosen. The method was used to design a 2.5 μA/V-cascoded OTA with minimum offset and current consumption in a 0.5 μm CMOS technology. Post layout Montecarlo simulations were performed to obtain an estimated offset of the circuit. The standard deviation obtained from the Montecarlo simulation was 3.94 mV while that expected from the design method was 3.86 mV. The total current consumption of the OTA is only 400 nA. Simulation results confirm the reliability of the presented design method.
| 2013 | |
| Electrónica | |
| Inglés | |
| Universidad de la República | |
| COLIBRI | |
| https://hdl.handle.net/20.500.12008/41770 | |
| Acceso abierto | |
| Licencia Creative Commons Atribución - No Comercial - Sin Derivadas (CC - By-NC-ND 4.0) |
| _version_ | 1807522938767802368 |
|---|---|
| author | Rossi Aicardi, Conrado |
| author2 | Veirano Núñez, Francisco Pérez Nicoli, Pablo Sebastián Aguirre, Pablo |
| author2_role | author author author |
| author_facet | Rossi Aicardi, Conrado Veirano Núñez, Francisco Pérez Nicoli, Pablo Sebastián Aguirre, Pablo |
| author_role | author |
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| collection | COLIBRI |
| dc.creator.none.fl_str_mv | Rossi Aicardi, Conrado Veirano Núñez, Francisco Pérez Nicoli, Pablo Sebastián Aguirre, Pablo |
| dc.date.accessioned.none.fl_str_mv | 2023-12-11T19:57:41Z |
| dc.date.available.none.fl_str_mv | 2023-12-11T19:57:41Z |
| dc.date.issued.es.fl_str_mv | 2013 |
| dc.date.submitted.es.fl_str_mv | 20231211 |
| dc.description.abstract.none.fl_txt_mv | A design method for ultra low power, low offset, symmetric OTAs is presented. The method is based on the gm/ID methodology and uses a model of MOS transistor valid in all the regions of operation which assures that the optimal operating point is chosen. The method was used to design a 2.5 μA/V-cascoded OTA with minimum offset and current consumption in a 0.5 μm CMOS technology. Post layout Montecarlo simulations were performed to obtain an estimated offset of the circuit. The standard deviation obtained from the Montecarlo simulation was 3.94 mV while that expected from the design method was 3.86 mV. The total current consumption of the OTA is only 400 nA. Simulation results confirm the reliability of the presented design method. |
| dc.description.es.fl_txt_mv | Trabajo presentado a 7th Argentine School of Micro-Nanoelectronics, Technology and Applications, Buenos Aires, Argentina, 2013 |
| dc.identifier.citation.es.fl_str_mv | Pérez Nicoli, P, Veirano, F, Rossi Aicardi, C, Aguirre, P. "Design method for an ultra low power, low offset, symmetric OTA," Publicado en 7th Argentine School of Micro-Nanoelectronics, Technology and Applications, Buenos Aires, Argentina, 2013, pp. 38-43. |
| dc.identifier.uri.none.fl_str_mv | https://hdl.handle.net/20.500.12008/41770 |
| dc.language.iso.none.fl_str_mv | en eng |
| dc.rights.license.none.fl_str_mv | Licencia Creative Commons Atribución - No Comercial - Sin Derivadas (CC - By-NC-ND 4.0) |
| dc.rights.none.fl_str_mv | info:eu-repo/semantics/openAccess |
| dc.source.none.fl_str_mv | reponame:COLIBRI instname:Universidad de la República instacron:Universidad de la República |
| dc.subject.other.es.fl_str_mv | Electrónica |
| dc.title.none.fl_str_mv | Design method for an ultra low power, low offset, symmetric OTA |
| dc.type.es.fl_str_mv | Ponencia |
| dc.type.none.fl_str_mv | info:eu-repo/semantics/conferenceObject |
| dc.type.version.none.fl_str_mv | info:eu-repo/semantics/publishedVersion |
| description | Trabajo presentado a 7th Argentine School of Micro-Nanoelectronics, Technology and Applications, Buenos Aires, Argentina, 2013 |
| eu_rights_str_mv | openAccess |
| format | conferenceObject |
| id | COLIBRI_b5df7057dd6163a75627c44f746b014b |
| identifier_str_mv | Pérez Nicoli, P, Veirano, F, Rossi Aicardi, C, Aguirre, P. "Design method for an ultra low power, low offset, symmetric OTA," Publicado en 7th Argentine School of Micro-Nanoelectronics, Technology and Applications, Buenos Aires, Argentina, 2013, pp. 38-43. |
| instacron_str | Universidad de la República |
| institution | Universidad de la República |
| instname_str | Universidad de la República |
| language | eng |
| language_invalid_str_mv | en |
| network_acronym_str | COLIBRI |
| network_name_str | COLIBRI |
| oai_identifier_str | oai:colibri.udelar.edu.uy:20.500.12008/41770 |
| publishDate | 2013 |
| reponame_str | COLIBRI |
| repository.mail.fl_str_mv | mabel.seroubian@seciu.edu.uy |
| repository.name.fl_str_mv | COLIBRI - Universidad de la República |
| repository_id_str | 4771 |
| rights_invalid_str_mv | Licencia Creative Commons Atribución - No Comercial - Sin Derivadas (CC - By-NC-ND 4.0) |
| spelling | 2023-12-11T19:57:41Z2023-12-11T19:57:41Z201320231211Pérez Nicoli, P, Veirano, F, Rossi Aicardi, C, Aguirre, P. "Design method for an ultra low power, low offset, symmetric OTA," Publicado en 7th Argentine School of Micro-Nanoelectronics, Technology and Applications, Buenos Aires, Argentina, 2013, pp. 38-43.https://hdl.handle.net/20.500.12008/41770Trabajo presentado a 7th Argentine School of Micro-Nanoelectronics, Technology and Applications, Buenos Aires, Argentina, 2013A design method for ultra low power, low offset, symmetric OTAs is presented. The method is based on the gm/ID methodology and uses a model of MOS transistor valid in all the regions of operation which assures that the optimal operating point is chosen. The method was used to design a 2.5 μA/V-cascoded OTA with minimum offset and current consumption in a 0.5 μm CMOS technology. Post layout Montecarlo simulations were performed to obtain an estimated offset of the circuit. The standard deviation obtained from the Montecarlo simulation was 3.94 mV while that expected from the design method was 3.86 mV. The total current consumption of the OTA is only 400 nA. Simulation results confirm the reliability of the presented design method.Made available in DSpace on 2023-12-11T19:57:41Z (GMT). No. of bitstreams: 5 PVRA13.pdf: 363628 bytes, checksum: 6b7616609545f9ba388953655ff0024c (MD5) license_text: 21936 bytes, checksum: 9833653f73f7853880c94a6fead477b1 (MD5) license_url: 49 bytes, checksum: 4afdbb8c545fd630ea7db775da747b2f (MD5) license_rdf: 23148 bytes, checksum: 9da0b6dfac957114c6a7714714b86306 (MD5) license.txt: 4244 bytes, checksum: 528b6a3c8c7d0c6e28129d576e989607 (MD5) Previous issue date: 2013enengLas obras depositadas en el Repositorio se rigen por la Ordenanza de los Derechos de la Propiedad Intelectual de la Universidad De La República. (Res. Nº 91 de C.D.C. de 8/III/1994 – D.O. 7/IV/1994) y por la Ordenanza del Repositorio Abierto de la Universidad de la República (Res. Nº 16 de C.D.C. de 07/10/2014)info:eu-repo/semantics/openAccessLicencia Creative Commons Atribución - No Comercial - Sin Derivadas (CC - By-NC-ND 4.0)ElectrónicaDesign method for an ultra low power, low offset, symmetric OTAPonenciainfo:eu-repo/semantics/conferenceObjectinfo:eu-repo/semantics/publishedVersionreponame:COLIBRIinstname:Universidad de la Repúblicainstacron:Universidad de la RepúblicaRossi Aicardi, ConradoVeirano Núñez, FranciscoPérez Nicoli, Pablo SebastiánAguirre, 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- Universidad de la Repúblicafalse |
| spellingShingle | Design method for an ultra low power, low offset, symmetric OTA Rossi Aicardi, Conrado Electrónica |
| status_str | publishedVersion |
| title | Design method for an ultra low power, low offset, symmetric OTA |
| title_full | Design method for an ultra low power, low offset, symmetric OTA |
| title_fullStr | Design method for an ultra low power, low offset, symmetric OTA |
| title_full_unstemmed | Design method for an ultra low power, low offset, symmetric OTA |
| title_short | Design method for an ultra low power, low offset, symmetric OTA |
| title_sort | Design method for an ultra low power, low offset, symmetric OTA |
| topic | Electrónica |
| url | https://hdl.handle.net/20.500.12008/41770 |
