On the functional test of the cache coherency logic in multi-core systems
Resumen:
Multi-core systems are becoming particularly common, due to the high performance they can deliver. Their performance strongly depends on the availability of effective cache controllers, able to guarantee (among others) the coherence of the caches of the different cores. This paper proposes a method for the test of the cache coherence logic existing within each core in a multi-core system, resorting to a functional approach, this means that the method is based on the generation of a suitable test program, to be run in a coordinated manner on the cores composing the system. The method is able to detect hardware defects affecting this logic. The method was validated on a LEON3 multicore system.
| 2015 | |
| Electrónica | |
| Inglés | |
| Universidad de la República | |
| COLIBRI | |
| https://hdl.handle.net/20.500.12008/42676 | |
| Acceso abierto | |
| Licencia Creative Commons Atribución - No Comercial - Sin Derivadas (CC - By-NC-ND 4.0) |
| _version_ | 1807522940541992960 |
|---|---|
| author | Pérez Acle, Julio |
| author2 | Cantoro, Riccardo Sánchez, Ernesto Sonza Reorda, Matteo |
| author2_role | author author author |
| author_facet | Pérez Acle, Julio Cantoro, Riccardo Sánchez, Ernesto Sonza Reorda, Matteo |
| author_role | author |
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| collection | COLIBRI |
| dc.creator.none.fl_str_mv | Pérez Acle, Julio Cantoro, Riccardo Sánchez, Ernesto Sonza Reorda, Matteo |
| dc.date.accessioned.none.fl_str_mv | 2024-02-26T19:52:35Z |
| dc.date.available.none.fl_str_mv | 2024-02-26T19:52:35Z |
| dc.date.issued.es.fl_str_mv | 2015 |
| dc.date.submitted.es.fl_str_mv | 20240223 |
| dc.description.abstract.none.fl_txt_mv | Multi-core systems are becoming particularly common, due to the high performance they can deliver. Their performance strongly depends on the availability of effective cache controllers, able to guarantee (among others) the coherence of the caches of the different cores. This paper proposes a method for the test of the cache coherence logic existing within each core in a multi-core system, resorting to a functional approach, this means that the method is based on the generation of a suitable test program, to be run in a coordinated manner on the cores composing the system. The method is able to detect hardware defects affecting this logic. The method was validated on a LEON3 multicore system. |
| dc.description.es.fl_txt_mv | Trabajo presentado en IEEE 6th Latin American Symposium on Circuits and Systems (LASCAS), Montevideo, Uruguay, 24-27 feb, 2015 |
| dc.identifier.citation.es.fl_str_mv | Acle, J.P, Cantoro, R, Sanchez, E, Reorda, M.S. "On the functional test of the cache coherency logic in multi-core systems" Publicado en: Proceedings of the IEEE 6th Latin American Symposium on Circuits and Systems (LASCAS), Montevideo, Uruguay, 2015, pp. 1-4, doi: 10.1109/LASCAS.2015.7250453. |
| dc.identifier.uri.none.fl_str_mv | https://hdl.handle.net/20.500.12008/42676 |
| dc.language.iso.none.fl_str_mv | en eng |
| dc.rights.license.none.fl_str_mv | Licencia Creative Commons Atribución - No Comercial - Sin Derivadas (CC - By-NC-ND 4.0) |
| dc.rights.none.fl_str_mv | info:eu-repo/semantics/openAccess |
| dc.source.none.fl_str_mv | reponame:COLIBRI instname:Universidad de la República instacron:Universidad de la República |
| dc.subject.other.es.fl_str_mv | Electrónica |
| dc.title.none.fl_str_mv | On the functional test of the cache coherency logic in multi-core systems |
| dc.type.es.fl_str_mv | Ponencia |
| dc.type.none.fl_str_mv | info:eu-repo/semantics/conferenceObject |
| dc.type.version.none.fl_str_mv | info:eu-repo/semantics/publishedVersion |
| description | Trabajo presentado en IEEE 6th Latin American Symposium on Circuits and Systems (LASCAS), Montevideo, Uruguay, 24-27 feb, 2015 |
| eu_rights_str_mv | openAccess |
| format | conferenceObject |
| id | COLIBRI_a0927e40d597d904221c728b6e46cbce |
| identifier_str_mv | Acle, J.P, Cantoro, R, Sanchez, E, Reorda, M.S. "On the functional test of the cache coherency logic in multi-core systems" Publicado en: Proceedings of the IEEE 6th Latin American Symposium on Circuits and Systems (LASCAS), Montevideo, Uruguay, 2015, pp. 1-4, doi: 10.1109/LASCAS.2015.7250453. |
| instacron_str | Universidad de la República |
| institution | Universidad de la República |
| instname_str | Universidad de la República |
| language | eng |
| language_invalid_str_mv | en |
| network_acronym_str | COLIBRI |
| network_name_str | COLIBRI |
| oai_identifier_str | oai:colibri.udelar.edu.uy:20.500.12008/42676 |
| publishDate | 2015 |
| reponame_str | COLIBRI |
| repository.mail.fl_str_mv | mabel.seroubian@seciu.edu.uy |
| repository.name.fl_str_mv | COLIBRI - Universidad de la República |
| repository_id_str | 4771 |
| rights_invalid_str_mv | Licencia Creative Commons Atribución - No Comercial - Sin Derivadas (CC - By-NC-ND 4.0) |
| spelling | 2024-02-26T19:52:35Z2024-02-26T19:52:35Z201520240223Acle, J.P, Cantoro, R, Sanchez, E, Reorda, M.S. "On the functional test of the cache coherency logic in multi-core systems" Publicado en: Proceedings of the IEEE 6th Latin American Symposium on Circuits and Systems (LASCAS), Montevideo, Uruguay, 2015, pp. 1-4, doi: 10.1109/LASCAS.2015.7250453.https://hdl.handle.net/20.500.12008/42676Trabajo presentado en IEEE 6th Latin American Symposium on Circuits and Systems (LASCAS), Montevideo, Uruguay, 24-27 feb, 2015Multi-core systems are becoming particularly common, due to the high performance they can deliver. Their performance strongly depends on the availability of effective cache controllers, able to guarantee (among others) the coherence of the caches of the different cores. This paper proposes a method for the test of the cache coherence logic existing within each core in a multi-core system, resorting to a functional approach, this means that the method is based on the generation of a suitable test program, to be run in a coordinated manner on the cores composing the system. The method is able to detect hardware defects affecting this logic. The method was validated on a LEON3 multicore system.Made available in DSpace on 2024-02-26T19:52:35Z (GMT). No. of bitstreams: 5 PCSS15.pdf: 241842 bytes, checksum: 2cfaa24b6eba4442b1ac721b711e3008 (MD5) license_text: 21936 bytes, checksum: 9833653f73f7853880c94a6fead477b1 (MD5) license_url: 49 bytes, checksum: 4afdbb8c545fd630ea7db775da747b2f (MD5) license_rdf: 23148 bytes, checksum: 9da0b6dfac957114c6a7714714b86306 (MD5) license.txt: 4244 bytes, checksum: 528b6a3c8c7d0c6e28129d576e989607 (MD5) Previous issue date: 2015enengLas obras depositadas en el Repositorio se rigen por la Ordenanza de los Derechos de la Propiedad Intelectual de la Universidad De La República. (Res. Nº 91 de C.D.C. de 8/III/1994 – D.O. 7/IV/1994) y por la Ordenanza del Repositorio Abierto de la Universidad de la República (Res. Nº 16 de C.D.C. de 07/10/2014)info:eu-repo/semantics/openAccessLicencia Creative Commons Atribución - No Comercial - Sin Derivadas (CC - By-NC-ND 4.0)ElectrónicaOn the functional test of the cache coherency logic in multi-core systemsPonenciainfo:eu-repo/semantics/conferenceObjectinfo:eu-repo/semantics/publishedVersionreponame:COLIBRIinstname:Universidad de la Repúblicainstacron:Universidad de la RepúblicaPérez Acle, JulioCantoro, RiccardoSánchez, ErnestoSonza Reorda, MatteoElectrónicaElectrónica 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- Universidad de la Repúblicafalse |
| spellingShingle | On the functional test of the cache coherency logic in multi-core systems Pérez Acle, Julio Electrónica |
| status_str | publishedVersion |
| title | On the functional test of the cache coherency logic in multi-core systems |
| title_full | On the functional test of the cache coherency logic in multi-core systems |
| title_fullStr | On the functional test of the cache coherency logic in multi-core systems |
| title_full_unstemmed | On the functional test of the cache coherency logic in multi-core systems |
| title_short | On the functional test of the cache coherency logic in multi-core systems |
| title_sort | On the functional test of the cache coherency logic in multi-core systems |
| topic | Electrónica |
| url | https://hdl.handle.net/20.500.12008/42676 |
