Variability-aware design method for a constant inversion level bias current generator
Resumen:
A model for estimating the dispersion in the output of a MOS-only, constant inversion level, current reference is presented. Based on such model, a design method is introduced that allows to minimize dispersion for a given layout complexity. The method was applied to five different designs producing currents from 2.4 nA to 4.2 nA (@ 300 K) and simulated dispersions with Cadence Spectre ranging from 1.3% to 1.5% (1 σ) while the model predicted dispersions from 1.2% to 1.4%.
| 2018 | |
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Current References MOS transistors Mismatch ACM Temperature effects |
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| Inglés | |
| Universidad de la República | |
| COLIBRI | |
| https://hdl.handle.net/20.500.12008/23858 | |
| Acceso abierto | |
| Licencia Creative Commons Atribución - No Comercial - Sin Derivadas (CC - By-NC-ND 4.0) |
| Sumario: | A model for estimating the dispersion in the output of a MOS-only, constant inversion level, current reference is presented. Based on such model, a design method is introduced that allows to minimize dispersion for a given layout complexity. The method was applied to five different designs producing currents from 2.4 nA to 4.2 nA (@ 300 K) and simulated dispersions with Cadence Spectre ranging from 1.3% to 1.5% (1 σ) while the model predicted dispersions from 1.2% to 1.4%. |
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